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Afterwards you can check whether your re-run was successful or not with the check_design command.

Beside the SYNOPSYS DESIGN COMPILER commands you have inserted into the synthesis script on your own, some

already pre-deﬁned commands exist. The section, displayed in the following, writes some reports about the synthesized

design into appropriate ﬁles:

# --------------------------------------------------------------------

# Generate Reports

# --------------------------------------------------------------------

report_timing > ./reports/timing.rpt

report_area -hierarchy > ./reports/area.rpt

report_register -nosplit > ./reports/registers.rpt

• The ﬁrst command creates a report about timing information and stores it in the ﬁle ./reports/timing.rpt.

• The second command generates a report about the required area of the design. The output gets stored in the ﬁle

./reports/area.rpt and is represented using a hierarchical view. The values presented in the area report are given in

µm

• The last row prints all registers within the design into the ﬁle ./reports/registers.rpt.

Note: The report commands, given in the synthesis script, represent only a small number of the available analysis

functionality of the SYNOPSYS DESIGN COMPILER. If you want to get a comprehensive list of the available report

commands within the SYNOPSYS DESIGN COMPILER, enter report into the DC Shell and then press TAB.

The second pre-deﬁned section in the synthesis script creates the Verilog netlist as described in Example I in this exer-

cise.

# --------------------------------------------------------------------

# Write Out Data

# --------------------------------------------------------------------

# Change names for Verilog.

change_names -rule verilog -hierarchy

# Write Verilog netlist.

write -hierarchy -format verilog -output ./netlists/graycnt.v

You may have recognized that for constrained timing paths, the command report_timing reports a value called slack.

If this value is positive, this means that the constraint set for the respective path has been met. If you get a value smaller

than zero, the respective path violates the timing constraint (i.e., has to be investigated further).

Student Task 3: Investigate the timing report a little bit more in detail and mark the critical path of the design within

the block diagram illustrated in Figure 6.

Does the design meet the timing requirements?

What is the value of the slack?

Show your results of this example (the ﬁnal synthesis script, the block diagram with the marked critical path, etc.) to

an assistant.

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